bssrdf
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c68fe36ae2
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WIP: cleanup; enhanced test case
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2025-10-25 21:57:39 -04:00 |
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bssrdf
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475f9879c5
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WIP: fixed another bug
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2025-10-25 20:24:14 -04:00 |
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bssrdf
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396f55831c
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WIP: bug fix
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2025-10-25 18:14:12 -04:00 |
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bssrdf
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610e41ae2d
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still debugging
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2025-10-25 11:10:39 -04:00 |
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bssrdf
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c45df12ee7
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this case is broken; to be debugged
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2025-10-24 22:40:34 -04:00 |
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bssrdf
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980ddc1e87
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properly use __CUDA_ARCH__ to protect the tensor path
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2025-10-24 21:56:58 -04:00 |
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bssrdf
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24b553204b
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WIP: fixed another bug
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2025-10-24 16:53:40 -04:00 |
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bssrdf
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6c90c20cb1
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WIP: bug fix
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2025-10-24 15:33:57 -04:00 |
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bssrdf
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be25be8ed3
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WIP: debugging tensor core kernel
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2025-10-24 14:24:26 -04:00 |
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bssrdf
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3f99818925
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unroll some loops
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2025-10-15 12:46:46 -04:00 |
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bssrdf
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b70cca2ea3
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add support for both NCHW and NHWC layouts
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2025-10-14 14:24:35 -04:00 |
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bssrdf
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2237722056
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added block variants; to be debugged
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2025-10-14 11:02:10 -04:00 |
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bssrdf
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c6255442bb
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minor updates
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2025-10-08 13:38:16 -04:00 |
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bssrdf
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53a2ccbe12
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minor update and add direct conv in benchmarking
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2025-09-24 21:48:20 -04:00 |
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bssrdf
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83a3b7d6a9
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Refactor conv2d_implicit_kernel for improved bitwise operations; add test for implicit convolution
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2025-09-06 17:26:19 -04:00 |