bssrdf
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3f99818925
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unroll some loops
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2025-10-15 12:46:46 -04:00 |
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bssrdf
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b70cca2ea3
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add support for both NCHW and NHWC layouts
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2025-10-14 14:24:35 -04:00 |
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bssrdf
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3e2f722d11
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fixed missing dilation
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2025-10-14 11:12:55 -04:00 |
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bssrdf
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2237722056
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added block variants; to be debugged
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2025-10-14 11:02:10 -04:00 |
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bssrdf
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16b0f0ae3c
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work in progress
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2025-10-13 18:41:30 -04:00 |
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bssrdf
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0ca43582e8
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reorder register tile loop
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2025-10-08 13:52:56 -04:00 |
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bssrdf
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53a2ccbe12
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minor update and add direct conv in benchmarking
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2025-09-24 21:48:20 -04:00 |
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bssrdf
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83a3b7d6a9
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Refactor conv2d_implicit_kernel for improved bitwise operations; add test for implicit convolution
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2025-09-06 17:26:19 -04:00 |
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bssrdf
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4b0f9d571f
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Refactor conv2d_implicit_kernel for improved readability and consistency; update parameter comments and remove unused code
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2025-09-05 08:29:57 -04:00 |
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bssrdf
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5ffe97be9c
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Fix boundary check in conv2d_implicit_kernel to include channel limits
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2025-09-04 15:32:29 -04:00 |
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bssrdf
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6d84cbb5ab
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Fix parameter order in conv2d_implicit and add comprehensive test cases for 2D convolution
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2025-09-03 15:45:09 -04:00 |
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bssrdf
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3877608dc0
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fix passing param as reference
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2025-09-03 12:45:19 -04:00 |
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bssrdf
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4d772873b9
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Add implicit convolution support for 2D tensors in CPU and CUDA implementations
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2025-09-03 11:29:14 -04:00 |
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bssrdf
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8a589317b6
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Add implicit GEMM convolution operation for 2D tensors in CUDA
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2025-09-02 22:47:41 -04:00 |