Merge 6f846df831 into 3bc8d2cf23
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fefe2ca0b0
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@ -90,8 +90,10 @@ static bool is_pow2(uint32_t x) { return x > 1 && (x & (x-1)) == 0; }
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#define VK_VENDOR_ID_AMD 0x1002
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#define VK_VENDOR_ID_APPLE 0x106b
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#define VK_VENDOR_ID_ARM 0x13B5
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#define VK_VENDOR_ID_INTEL 0x8086
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#define VK_VENDOR_ID_NVIDIA 0x10de
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#define VK_VENDOR_ID_QUALCOMM 0x5143
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#define VK_DEVICE_DESCRIPTOR_POOL_SIZE 256
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@ -3035,6 +3037,25 @@ static void ggml_vk_load_shaders(vk_device& device) {
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// Xe2/Xe3 with coopmat enabled - warptile performance tuning
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l_warptile = { 512, 128, 128, 16, subgroup_size_8, 32, 2, tm_m, tn_m, tk_m, subgroup_size_8 };
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l_warptile_mmq = { 512, 128, 128, 32, subgroup_size_8, 32, 2, tm_m, tn_m, tk_m, subgroup_size_8 };
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} else if (device->vendor_id == VK_VENDOR_ID_QUALCOMM) {
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uint32_t s = device->subgroup_size;
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m_warptile = m_warptile_mmq = m_warptile_mmq_int = m_warptile_mmq_k = m_warptile_mmq_int_k =
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m_warptile_id = m_warptile_mmqid = m_warptile_mmqid_int = m_warptile_mmqid_int_k =
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{ 64, 64, 64, s, s, 16, 8, 8, 1, 1, s };
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s_warptile = s_warptile_mmq = s_warptile_mmq_int = s_warptile_mmq_k = s_warptile_mmq_int_k =
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s_warptile_id = s_warptile_mmqid = s_warptile_mmqid_int = s_warptile_mmqid_int_k =
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{ 32, 32, 64, s, s, 16, 8, 8, 1, 1, s };
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} else if (device->vendor_id == VK_VENDOR_ID_ARM && device->subgroup_size >= 16) {
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uint32_t s = device->subgroup_size;
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s_warptile = s_warptile_mmq = s_warptile_mmq_int = s_warptile_mmq_k = s_warptile_mmq_int_k =
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s_warptile_id = s_warptile_mmqid = s_warptile_mmqid_int = s_warptile_mmqid_int_k =
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{ 32, 32, 64, s, s, 16, 4, 4, 1, 1, s };
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m_warptile = m_warptile_mmq = m_warptile_mmq_int = m_warptile_mmq_k = m_warptile_mmq_int_k =
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m_warptile_id = m_warptile_mmqid = m_warptile_mmqid_int = m_warptile_mmqid_int_k =
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{ 64, 64, 64, s, s, 16, 4, 4, 1, 1, s };
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l_warptile = l_warptile_mmq = l_warptile_mmq_int = l_warptile_mmq_k = l_warptile_mmq_int_k =
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l_warptile_id = l_warptile_mmqid = l_warptile_mmqid_int = l_warptile_mmqid_int_k =
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{ 64, 64, 64, s, s, 16, 4, 4, 1, 1, s };
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}
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l_mmq_wg_denoms = l_wg_denoms = {128, 128, 1 };
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@ -3044,6 +3065,10 @@ static void ggml_vk_load_shaders(vk_device& device) {
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m_align = 64;
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s_align = 32;
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if (device->vendor_id == VK_VENDOR_ID_QUALCOMM) {
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m_align = 128;
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}
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for (uint32_t i = 0; i < GGML_TYPE_COUNT; ++i) {
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ggml_type t = (ggml_type)i;
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// Disable medium and large matrix multiplication if not enough shared memory is available
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@ -3059,6 +3084,8 @@ static void ggml_vk_load_shaders(vk_device& device) {
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device->mul_mat_l[i] = false;
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}
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// Disable mul_mat_id if not enough shared memory is available
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if (!ggml_vk_matmul_shmem_support(device, s_warptile_mmqid, true, t)) {
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device->mul_mat_id_s[i] = false;
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@ -4690,9 +4717,24 @@ static vk_device ggml_vk_get_device(size_t idx) {
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// Limit batching of allocations to 1GB by default to avoid fragmentation issues
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device->suballocation_block_size = 1024*1024*1024;
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}
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if (device->vendor_id == VK_VENDOR_ID_ARM) {
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// ARM Mali optimization: disable fp16-matrix to prevent crashes, limit memory blocks
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device->coopmat_support = false;
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device->suballocation_block_size = 256 * 1024 * 1024;
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} else if (device->vendor_id == VK_VENDOR_ID_QUALCOMM) {
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// Qualcomm Adreno optimization: disable fp16-matrix and int8-dotprod to prevent crashes, limit memory blocks
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device->coopmat_support = false;
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device->integer_dot_product = false;
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device->suballocation_block_size = 256 * 1024 * 1024;
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}
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device->suballocation_block_size = std::min(device->suballocation_block_size, device->max_memory_allocation_size);
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device->subgroup_size = subgroup_props.subgroupSize;
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if (device->vendor_id == VK_VENDOR_ID_QUALCOMM && device->subgroup_size > 64) {
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VK_LOG_INFO("ggml_vulkan: clamping subgroup size to 64 for Qualcomm");
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device->subgroup_size = 64;
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}
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device->subgroup_size_log2 = uint32_t(log2f(float(device->subgroup_size)));
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device->uma = device->properties.deviceType == vk::PhysicalDeviceType::eIntegratedGpu;
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if (sm_builtins) {
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@ -5168,6 +5210,15 @@ static vk_device ggml_vk_get_device(size_t idx) {
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device->mul_mat_id_m[i] = true;
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device->mul_mat_id_s[i] = true;
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break;
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case VK_VENDOR_ID_ARM:
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case VK_VENDOR_ID_QUALCOMM:
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device->mul_mat_l[i] = false;
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device->mul_mat_id_l[i] = false;
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device->mul_mat_m[i] = true;
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device->mul_mat_s[i] = true;
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device->mul_mat_id_m[i] = true;
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device->mul_mat_id_s[i] = true;
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break;
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case VK_VENDOR_ID_APPLE:
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device->mul_mat_l[i] = false;
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device->mul_mat_m[i] = true;
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@ -13761,6 +13812,9 @@ static ggml_status ggml_backend_vk_graph_compute(ggml_backend_t backend, ggml_cg
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// (and scaled down based on model size, so smaller models submit earlier).
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// Also submit at least every 100 nodes, in case there are workloads without as much matmul.
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int nodes_per_submit = 100;
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if (ctx->device->vendor_id == VK_VENDOR_ID_QUALCOMM) {
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nodes_per_submit = 1000;
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}
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int submitted_nodes = 0;
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int submit_count = 0;
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uint64_t mul_mat_bytes = 0;
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