q8_0 repack GEMV implementations
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@ -2629,7 +2629,40 @@ void ggml_gemv_q8_0_4x4_q8_0(int n,
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UNUSED(blocklen);
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#if defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD)
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// TODO: Implement ARM NEON DOTPROD kernel for q8_0 × q8_0 GEMV
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const block_q8_0x4 * b_ptr = (const block_q8_0x4 *) vx;
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for (int c = 0; c < nc; c += ncols_interleaved) {
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const block_q8_0 * a_ptr = (const block_q8_0 *) vy;
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float32x4_t acc = vdupq_n_f32(0);
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for (int b = 0; b < nb; b++) {
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int8x16x4_t b_low = vld1q_s8_x4((const int8_t *) b_ptr->qs);
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int8x16x4_t b_high = vld1q_s8_x4((const int8_t *) b_ptr->qs + 64);
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float16x4_t bd = vld1_f16((const __fp16 *) b_ptr->d);
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int8x16x2_t a = vld1q_s8_x2(a_ptr->qs);
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float16x4_t ad = vld1_dup_f16((const __fp16 *) &a_ptr->d);
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int32x4_t ret = vdupq_n_s32(0);
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ret = vdotq_laneq_s32(ret, b_low.val[0], a.val[0], 0);
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ret = vdotq_laneq_s32(ret, b_low.val[1], a.val[0], 1);
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ret = vdotq_laneq_s32(ret, b_low.val[2], a.val[0], 2);
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ret = vdotq_laneq_s32(ret, b_low.val[3], a.val[0], 3);
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ret = vdotq_laneq_s32(ret, b_high.val[0], a.val[1], 0);
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ret = vdotq_laneq_s32(ret, b_high.val[1], a.val[1], 1);
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ret = vdotq_laneq_s32(ret, b_high.val[2], a.val[1], 2);
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ret = vdotq_laneq_s32(ret, b_high.val[3], a.val[1], 3);
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acc = vfmaq_f32(acc, vcvtq_f32_s32(ret), vmulq_f32(vcvt_f32_f16(ad), vcvt_f32_f16(bd)));
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a_ptr++;
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b_ptr++;
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}
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vst1q_f32(s, acc);
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s += ncols_interleaved;
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}
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return;
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#endif // defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD)
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ggml_gemv_q8_0_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc);
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}
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@ -2653,9 +2686,53 @@ void ggml_gemv_q8_0_4x8_q8_0(int n,
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UNUSED(ncols_interleaved);
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UNUSED(blocklen);
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#if defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8)
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// TODO: Implement ARM NEON I8MM kernel for q8_0 × q8_0 GEMV
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#endif // defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8)
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#if defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD)
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const block_q8_0x4 * b_ptr = (const block_q8_0x4 *) vx;
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for (int c = 0; c < nc; c += ncols_interleaved) {
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const block_q8_0 * a_ptr = (const block_q8_0 *) vy;
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float32x4_t acc = vdupq_n_f32(0);
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for (int b = 0; b < nb; b++) {
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int8x16x4_t b_low = vld1q_s8_x4((const int8_t *) b_ptr->qs);
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int8x16x4_t b_high = vld1q_s8_x4((const int8_t *) b_ptr->qs + 64);
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float16x4_t bd = vld1_f16((const __fp16 *) b_ptr->d);
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int8x8x4_t a_chunks = vld1_s8_x4(a_ptr->qs);
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int8x16_t a0 = vcombine_s8(a_chunks.val[0], a_chunks.val[0]);
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int8x16_t a1 = vcombine_s8(a_chunks.val[1], a_chunks.val[1]);
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int8x16_t a2 = vcombine_s8(a_chunks.val[2], a_chunks.val[2]);
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int8x16_t a3 = vcombine_s8(a_chunks.val[3], a_chunks.val[3]);
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float16x4_t ad = vld1_dup_f16((const __fp16 *) &a_ptr->d);
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int32x4_t ret0 = vdupq_n_s32(0);
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int32x4_t ret1 = vdupq_n_s32(0);
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// 0..7
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ret0 = vdotq_s32(ret0, b_low.val[0], a0);
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ret1 = vdotq_s32(ret1, b_low.val[1], a0);
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// 8..15
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ret0 = vdotq_s32(ret0, b_low.val[2], a1);
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ret1 = vdotq_s32(ret1, b_low.val[3], a1);
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// 16..23
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ret0 = vdotq_s32(ret0, b_high.val[0], a2);
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ret1 = vdotq_s32(ret1, b_high.val[1], a2);
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// 24..31
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ret0 = vdotq_s32(ret0, b_high.val[2], a3);
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ret1 = vdotq_s32(ret1, b_high.val[3], a3);
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int32x4_t ret = vpaddq_s32(ret0, ret1);
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acc = vfmaq_f32(acc, vcvtq_f32_s32(ret), vmulq_f32(vcvt_f32_f16(ad), vcvt_f32_f16(bd)));
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a_ptr++;
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b_ptr++;
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}
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vst1q_f32(s, acc);
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s += ncols_interleaved;
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}
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return;
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#endif // defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD)
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ggml_gemv_q8_0_4x8_q8_0_generic(n, s, bs, vx, vy, nr, nc);
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}
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@ -2706,7 +2783,6 @@ void ggml_gemm_q8_0_4x8_q8_0(int n,
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UNUSED(blocklen);
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#if defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8)
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// TODO: Implement ARM NEON I8MM kernel for q8_0 × q8_0 GEMM
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#endif // defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8)
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ggml_gemm_q8_0_4x8_q8_0_generic(n, s, bs, vx, vy, nr, nc);
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}
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