vulkan: optimize UMA memory allocation and fix ARM specific tuning logic
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@ -90,6 +90,7 @@ static bool is_pow2(uint32_t x) { return x > 1 && (x & (x-1)) == 0; }
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#define VK_VENDOR_ID_AMD 0x1002
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#define VK_VENDOR_ID_APPLE 0x106b
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#define VK_VENDOR_ID_ARM 0x13B5
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#define VK_VENDOR_ID_INTEL 0x8086
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#define VK_VENDOR_ID_NVIDIA 0x10de
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@ -2528,7 +2529,8 @@ static vk_buffer ggml_vk_create_buffer_device(vk_device& device, size_t size) {
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vk::MemoryPropertyFlagBits::eDeviceLocal});
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} else if (device->uma) {
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// Fall back to host memory type
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buf = ggml_vk_create_buffer(device, size, {vk::MemoryPropertyFlagBits::eDeviceLocal,
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buf = ggml_vk_create_buffer(device, size, {vk::MemoryPropertyFlagBits::eDeviceLocal | vk::MemoryPropertyFlagBits::eHostVisible | vk::MemoryPropertyFlagBits::eHostCoherent,
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vk::MemoryPropertyFlagBits::eDeviceLocal,
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vk::MemoryPropertyFlagBits::eHostVisible | vk::MemoryPropertyFlagBits::eHostCoherent});
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} else if (device->disable_host_visible_vidmem) {
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if (device->allow_sysmem_fallback) {
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@ -2930,7 +2932,11 @@ static void ggml_vk_load_shaders(vk_device& device) {
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s_warptile_mmqid_int_k = { mul_mat_subgroup_size_32, 32, 32, 32, 32, 32, 1, 2, 1, 1, mul_mat_subgroup_size_16 };
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// chip specific tuning
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if ((device->architecture == AMD_GCN) && (device->driver_id != vk::DriverId::eAmdProprietary)) {
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if (device->vendor_id == VK_VENDOR_ID_ARM) {
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m_warptile_mmq = m_warptile_mmq_int = { 64, 64, 64, 16, 16, 32, 2, 2, 2, 1, 16 };
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m_warptile = { 64, 64, 64, 16, 16, 32, 2, 2, 2, 1, 16 };
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m_warptile_id = m_warptile_mmqid = { 64, 64, 64, 16, 16, 32, 2, 2, 2, 1, 16 };
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} else if ((device->architecture == AMD_GCN) && (device->driver_id != vk::DriverId::eAmdProprietary)) {
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m_warptile_mmq = m_warptile_mmq_int = { 256, 64, 64, 32, 16, 16, 2, 2, 2, 1, 16 };
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m_warptile_mmqid = m_warptile_mmqid_int = { 256, 64, 64, 32, 16, 16, 2, 2, 2, 1, 16 };
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}
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@ -4487,6 +4493,14 @@ static vk_device ggml_vk_get_device(size_t idx) {
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device->vendor_id = device->properties.vendorID;
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device->driver_id = driver_props.driverID;
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if (device->vendor_id == VK_VENDOR_ID_ARM) {
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// Forcing FP32 path as it currently provides better performance on Mali G720.
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// This is a simplified approach while deeper ARM-specific vec2 SIMD optimizations are investigated.
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fp16_storage = false;
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fp16_compute = false;
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bfloat16_support = false;
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}
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// Implementing the async backend interfaces seems broken on older Intel HW,
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// see https://github.com/ggml-org/llama.cpp/issues/17302.
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device->support_async = (device->vendor_id != VK_VENDOR_ID_INTEL ||
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@ -4521,6 +4535,9 @@ static vk_device ggml_vk_get_device(size_t idx) {
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if (GGML_VK_SUBALLOCATION_BLOCK_SIZE != nullptr) {
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device->suballocation_block_size = std::stoull(GGML_VK_SUBALLOCATION_BLOCK_SIZE);
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} else if (device->vendor_id == VK_VENDOR_ID_ARM) {
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// Limit batching of allocations to 256MB on Mali GPUs to avoid fragmentation issues
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device->suballocation_block_size = 256 * 1024 * 1024;
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} else {
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// Limit batching of allocations to 1GB by default to avoid fragmentation issues
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device->suballocation_block_size = 1024*1024*1024;
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