Merge 52f43fb962 into 2973a65ecb
This commit is contained in:
commit
ead19dc2eb
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@ -2161,9 +2161,15 @@ static bool ggml_hexagon_supported_activations(const struct ggml_hexagon_session
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}
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// src0, src1 & dst must be mapped to the same session
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if(src1){
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if (!hex_supported_buffer(sess, src0, src1, dst)) {
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return false;
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}
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}else{
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if (!hex_supported_buffer(sess, src0, dst)) {
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return false;
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}
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}
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return true;
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}
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@ -2662,6 +2668,10 @@ static void ggml_hexagon_unary(const struct ggml_tensor * op, uint32_t flags) {
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req.op = HTP_OP_UNARY_SILU;
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supported = true;
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}
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else if (ggml_get_unary_op(dst) == GGML_UNARY_OP_GELU){
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req.op = HTP_OP_UNARY_GELU;
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supported = true;
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}
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break;
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case GGML_OP_GLU:
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@ -2677,6 +2687,7 @@ static void ggml_hexagon_unary(const struct ggml_tensor * op, uint32_t flags) {
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case GGML_OP_SOFT_MAX:
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req.op = HTP_OP_SOFTMAX;
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supported = true;
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break;
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default:
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break;
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@ -2956,6 +2967,8 @@ static ggml_status ggml_backend_hexagon_graph_compute(ggml_backend_t backend, gg
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case GGML_OP_UNARY:
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if (ggml_get_unary_op(node) == GGML_UNARY_OP_SILU) {
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ggml_hexagon_unary(node, flags);
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} else if (ggml_get_unary_op(node) == GGML_UNARY_OP_GELU) {
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ggml_hexagon_unary(node, flags);
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}
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break;
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case GGML_OP_GLU:
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@ -3254,7 +3267,6 @@ static bool ggml_backend_hexagon_device_supports_op(ggml_backend_dev_t dev, cons
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auto sess = static_cast<ggml_hexagon_session *>(dev->context);
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bool supp = false;
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switch (op->op) {
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case GGML_OP_NONE:
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case GGML_OP_RESHAPE:
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@ -3294,6 +3306,9 @@ static bool ggml_backend_hexagon_device_supports_op(ggml_backend_dev_t dev, cons
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if (ggml_get_unary_op(op) == GGML_UNARY_OP_SILU) {
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supp = ggml_hexagon_supported_activations(sess, op);
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}
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else if (ggml_get_unary_op(op) == GGML_UNARY_OP_GELU){
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supp = ggml_hexagon_supported_activations(sess, op);
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}
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break;
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case GGML_OP_GLU:
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@ -255,6 +255,92 @@ static void glu_swiglu_oai_fp32_per_thread(const struct htp_tensor * src0,
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src1->ne[3], dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], (unsigned) HAP_perf_qtimer_count_to_us(t2 - t1));
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}
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static void unary_gelu_fp32_per_thread(const struct htp_tensor * src0,
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struct htp_tensor * dst,
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const int32_t * op_params,
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struct htp_spad * src0_spad,
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struct htp_spad * dst_spad,
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uint32_t nth,
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uint32_t ith,
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uint32_t src0_nrows_per_thread) {
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htp_act_preamble2;
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uint64_t t1, t2;
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t1 = HAP_perf_get_qtimer_count();
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const size_t src0_row_size = nb01;
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const size_t dst_row_size = nb1;
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const uint32_t src0_nrows = ne01 * ne02 * ne03;
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const uint32_t src0_start_row = src0_nrows_per_thread * ith;
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const uint32_t src0_end_row = MIN(src0_start_row + src0_nrows_per_thread, src0_nrows);
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// no work for this thread
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if (src0_start_row >= src0_end_row) {
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return;
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}
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int is_aligned = 1;
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int opt_path = 0;
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if (!htp_is_aligned((void *) src0->data, VLEN) || !htp_is_aligned((void *) dst->data, VLEN)) {
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is_aligned = 0;
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FARF(HIGH, "silu-f32: unaligned addresses in elementwise op, possibly slower execution\n");
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}
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if ((1 == is_aligned) && !(nb01 & (VLEN - 1))) {
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opt_path = 1;
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}
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const uint8_t * restrict data_src0 = (const uint8_t *) src0->data;
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uint8_t * restrict data_dst = (uint8_t *) dst->data;
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uint8_t * restrict src0_spad_data = src0_spad->data + (ith * src0_row_size);
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uint8_t * restrict dst_spad_data = dst_spad->data + (ith * dst_row_size);
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const int BLOCK = 8;
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for (uint32_t ir = src0_start_row; ir < src0_end_row; ir += BLOCK) {
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const uint32_t block_end = MIN(ir + BLOCK, src0_end_row);
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// Prefetch next block
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if (block_end < src0_end_row) {
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const float * restrict prefetch_ptr = (float *) (data_src0 + (block_end * src0_row_size));
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htp_l2fetch(prefetch_ptr, 1, block_end * src0_row_size, src0_row_size);
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}
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// Process rows in current block
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for (uint32_t ib = ir; ib < block_end; ib++) {
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const float * restrict src0 = (float *) (data_src0 + (ib * src0_row_size));
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float * restrict dst = (float *) (data_dst + (ib * dst_row_size));
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// gelu = x * sigmoid(1.702 * x) // current implementation
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if (1 == opt_path) {
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hvx_mul_scalar_f32( (const uint8_t *) src0, (float)1.702, (uint8_t *) src0_spad_data, ne0);
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hvx_fast_sigmoid_f32((const uint8_t *) src0_spad_data, (uint8_t *) src0_spad_data, ne0);
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hvx_mul_f32_opt((const uint8_t *) src0, src0_spad_data, (uint8_t *) dst, ne0);
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}
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else {
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hvx_mul_scalar_f32( (const uint8_t *) src0, (float)1.702, (uint8_t *) src0_spad_data, ne0);
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hvx_sigmoid_f32((const uint8_t *) src0_spad_data, (uint8_t *) src0_spad_data, ne0);
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hvx_mul_f32((const uint8_t *) src0, src0_spad_data, (uint8_t *) dst, ne0);
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}
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}
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}
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t2 = HAP_perf_get_qtimer_count();
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FARF(HIGH, "gelu-f32 %d/%d/%d: %ux%ux%ux%u (%u:%u) -> %ux%ux%ux%u usec %u\n", ith, nth, opt_path, ne00, ne01, ne02,
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ne03, src0_start_row, src0_end_row, ne0, ne1, ne2, ne3, (unsigned) HAP_perf_qtimer_count_to_us(t2 - t1));
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}
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static void unary_gelu_fp32(unsigned int n, unsigned int i, void * data) {
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struct htp_ops_context * octx = (struct htp_ops_context *) data;
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unary_gelu_fp32_per_thread(&octx->src0, &octx->dst, octx->op_params, &octx->src0_spad, &octx->dst_spad, n, i,
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octx->src0_nrows_per_thread);
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}
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static void unary_silu_fp32_per_thread(const struct htp_tensor * src0,
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struct htp_tensor * dst,
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const int32_t * op_params,
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@ -371,7 +457,10 @@ static int execute_op_activations_fp32(struct htp_ops_context * octx) {
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act_op_func = glu_swiglu_oai_fp32;
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op_type = "swiglu-oai-f32";
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break;
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case HTP_OP_UNARY_GELU:
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act_op_func = unary_gelu_fp32;
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op_type = "gelu-f32";
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break;
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default:
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FARF(ERROR, "Unsupported activations Op %u\n", octx->op);
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return HTP_STATUS_NO_SUPPORT;
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@ -51,11 +51,12 @@ enum htp_op {
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HTP_OP_MUL_MAT_ID = 5,
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HTP_OP_RMS_NORM = 6,
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HTP_OP_UNARY_SILU = 7,
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HTP_OP_GLU_SWIGLU = 8,
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HTP_OP_GLU_SWIGLU_OAI = 9,
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HTP_OP_SOFTMAX = 10,
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HTP_OP_ADD_ID = 11,
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HTP_OP_ROPE = 12,
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HTP_OP_UNARY_GELU = 8,
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HTP_OP_GLU_SWIGLU = 9,
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HTP_OP_GLU_SWIGLU_OAI = 10,
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HTP_OP_SOFTMAX = 11,
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HTP_OP_ADD_ID = 12,
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HTP_OP_ROPE = 13,
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INVALID
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};
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@ -49,6 +49,8 @@ void hvx_mul_f32(const uint8_t * restrict src0,
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FARF(HIGH, "hvx_mul_f32: unaligned loop in hvx op, possibly slower execution\n");
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}
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bool handled_leftover = false;
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if (0 == unaligned_loop) {
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HVX_Vector * restrict vec_in1 = (HVX_Vector *) src0;
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HVX_Vector * restrict vec_in2 = (HVX_Vector *) src1;
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@ -60,18 +62,65 @@ void hvx_mul_f32(const uint8_t * restrict src0,
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*vec_out++ = Q6_Vsf_equals_Vqf32(v);
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}
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} else {
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int step_of_1 = num_elems_whole >> 5; // divby 32, because 32 float = 128 bytes per HVX vector
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int leftover_size = left_over * sizeof(float);
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HVX_Vector * restrict vec_in1 = (HVX_Vector *) src0;
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HVX_Vector * restrict vec_in2 = (HVX_Vector *) src1;
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HVX_UVector * restrict vec_out = (HVX_UVector *) dst;
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HVX_Vector slinep;
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HVX_Vector slinec;
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HVX_Vector sline;
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HVX_Vector sline2p;
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HVX_Vector sline2c;
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HVX_Vector sline2;
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slinep = *vec_in1++;
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sline2p = *vec_in2++;
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#pragma unroll(4)
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for (int i = 0; i < num_elems_whole; i += VLEN_FP32) {
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HVX_Vector in1 = *(HVX_UVector *) (src0 + i * SIZEOF_FP32);
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HVX_Vector in2 = *(HVX_UVector *) (src1 + i * SIZEOF_FP32);
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for(int i = step_of_1 -1; i> 0; i--){
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slinec = *vec_in1++;
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sline2c = *vec_in2++;
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sline = Q6_V_valign_VVR(slinec, slinep, (size_t) src0);
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sline2 = Q6_V_valign_VVR(sline2c, sline2p, (size_t) src1);
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HVX_Vector out = Q6_Vqf32_vmpy_VsfVsf(in1, in2);
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*(HVX_UVector *) (dst + i * SIZEOF_FP32) = Q6_Vsf_equals_Vqf32(out);
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}
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*((HVX_UVector *)(vec_out++)) =Q6_Vsf_equals_Vqf32( Q6_Vqf32_vmpy_VsfVsf(sline, sline2));
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slinep = slinec;
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sline2p = sline2c;
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}
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if(step_of_1 > 1){
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slinec = htp_is_aligned(vec_in1, VLEN) && left_over == 0 ? slinep : *vec_in1++;
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sline2c = htp_is_aligned(vec_in2, VLEN) && left_over == 0 ? sline2p : *vec_in2++;
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sline = Q6_V_valign_VVR(slinec, slinep, (size_t) src0);
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sline2 = Q6_V_valign_VVR(sline2c, sline2p, (size_t) src1);
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*((HVX_UVector *)(vec_out++)) =Q6_Vsf_equals_Vqf32( Q6_Vqf32_vmpy_VsfVsf(sline, sline2));
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slinep = slinec;
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sline2p = sline2c;
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}
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if(left_over > 0 ){
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slinec = (is_in_one_chunk(vec_in1, leftover_size, VLEN)
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? slinep
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: *vec_in1++);
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sline = Q6_V_valign_VVR(slinec, slinep, (size_t) src0);
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sline2c = (is_in_one_chunk(vec_in2, leftover_size, VLEN)
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? sline2p
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: *vec_in2++);
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sline2 = Q6_V_valign_VVR(sline2c, sline2p, (size_t) src1);
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HVX_Vector out = Q6_Vqf32_vmpy_VsfVsf(sline, sline2);
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hvx_vec_store_u(vec_out, leftover_size, Q6_Vsf_equals_Vqf32(out));
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handled_leftover = true;
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}
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}
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if (left_over > 0 && !handled_leftover) {
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const float * src0f = (const float *) src0 + num_elems_whole;
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const float * src1f = (const float *) src1 + num_elems_whole;
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float * dstf = (float *) dst + num_elems_whole;
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@ -464,7 +513,7 @@ void hvx_mul_scalar_f32(const uint8_t * restrict src, const float val, uint8_t *
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}
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HVX_Vector val_vec = hvx_vec_splat_fp32(val);
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bool handled_leftover = false;
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if (0 == unaligned_loop) {
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HVX_Vector * restrict vec_in1 = (HVX_Vector *) src;
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HVX_Vector * restrict vec_out = (HVX_Vector *) dst;
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@ -475,17 +524,53 @@ void hvx_mul_scalar_f32(const uint8_t * restrict src, const float val, uint8_t *
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*vec_out++ = Q6_Vsf_equals_Vqf32(v);
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}
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} else {
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int step_of_1 = num_elems >> 5; // divby 32, because 32 float = 128 bytes per HVX vector
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int leftover_size = left_over * sizeof(float);
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HVX_Vector * input_v_ptr = (HVX_Vector *) src;
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HVX_UVector * output_v_ptr = (HVX_UVector *) dst;
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HVX_Vector slinep;
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HVX_Vector slinec;
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HVX_Vector sline;
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slinep = *input_v_ptr++;
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#pragma unroll(4)
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for (int i = 0; i < num_elems_whole; i += VLEN_FP32) {
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HVX_Vector in = *(HVX_UVector *) (src + i * SIZEOF_FP32);
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for(int i = step_of_1 - 1; i > 0; i--){
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slinec = *input_v_ptr++;
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sline = Q6_V_valign_VVR(slinec, slinep, (size_t) src);
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*((HVX_UVector *)(output_v_ptr++)) = Q6_Vsf_equals_Vqf32( Q6_Vqf32_vmpy_VsfVsf(sline, val_vec));
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/* Prepare slinep for next iteration */
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slinep = slinec;
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}
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HVX_Vector out = Q6_Vqf32_vmpy_VsfVsf(in, val_vec);
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if(step_of_1 > 0){
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*(HVX_UVector *) (dst + i * SIZEOF_FP32) = Q6_Vsf_equals_Vqf32(out);
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slinec = htp_is_aligned(input_v_ptr, VLEN) && left_over == 0 ? slinep : *input_v_ptr++;
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sline = Q6_V_valign_VVR(slinec, slinep, (size_t) src);
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*((HVX_UVector *)(output_v_ptr++)) = Q6_Vsf_equals_Vqf32( Q6_Vqf32_vmpy_VsfVsf(sline, val_vec));
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slinep = slinec;
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}
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if(leftover_size > 0){
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slinec = (is_in_one_chunk(input_v_ptr, leftover_size, VLEN)
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? slinep
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: *input_v_ptr++);
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sline = Q6_V_valign_VVR(slinec, slinep, (size_t) src);
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HVX_Vector sout = Q6_Vsf_equals_Vqf32( Q6_Vqf32_vmpy_VsfVsf(sline, val_vec));
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hvx_vec_store_u(output_v_ptr, leftover_size, sout);
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handled_leftover = true;
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}
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}
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if (left_over > 0) {
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if (left_over > 0 && !handled_leftover) {
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const float * srcf = (const float *) src + num_elems_whole;
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float * dstf = (float *) dst + num_elems_whole;
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|
|
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@ -265,12 +265,16 @@ static inline void hvx_bcast_fp32_a(uint8_t * restrict dst, float elem, uint32_t
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}
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}
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/* Return whether 'n' elements from vector are in the one chunk of 'chunk_size'. */
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static __attribute__((always_inline)) int32_t is_in_one_chunk(void * addr, uint32_t n, uint32_t chunk_size) {
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uint32_t left_off = (size_t) addr & (chunk_size - 1);
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uint32_t right_off = left_off + n;
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return right_off <= chunk_size;
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}
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static void hvx_vec_dump_fp16_n(char * pref, HVX_Vector v, uint32_t n) {
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HVX_VectorAlias u = { .v = v };
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|
@ -994,6 +998,65 @@ static inline void hvx_fast_sigmoid_f32(const uint8_t * restrict src, uint8_t *
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}
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}
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static inline void hvx_sigmoid_f32(const uint8_t * restrict src, uint8_t * restrict dst, const int num_elems){
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int step_of_1 = num_elems >> 5; // divby 32, because 32 float = 128 bytes per HVX vector
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||||
int leftover = num_elems - (step_of_1 * VLEN_FP32);
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||||
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||||
int32_t leftover_size = leftover * sizeof(float);
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||||
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static const float kMinExp = -87.f; // 0
|
||||
static const float kMaxExp = 87.f; // 1
|
||||
|
||||
const HVX_Vector one = hvx_vec_splat_fp32(1.f);
|
||||
const HVX_Vector max_exp = hvx_vec_splat_fp32(kMaxExp);
|
||||
const HVX_Vector min_exp = hvx_vec_splat_fp32(kMinExp);
|
||||
|
||||
const float *input = (float *)src;
|
||||
float *output = (float *)dst;
|
||||
|
||||
HVX_Vector * input_v_ptr = (HVX_Vector *) input;
|
||||
HVX_UVector * output_v_ptr = (HVX_UVector *) output;
|
||||
|
||||
|
||||
HVX_Vector slinep;
|
||||
HVX_Vector slinec;
|
||||
HVX_Vector sline;
|
||||
|
||||
|
||||
slinep = *input_v_ptr++;
|
||||
#pragma unroll(4)
|
||||
for(int i = step_of_1 -1; i> 0; i--){
|
||||
slinec = *input_v_ptr++;
|
||||
sline = Q6_V_valign_VVR(slinec, slinep, (size_t) input);
|
||||
*((HVX_UVector *)(output_v_ptr++)) = hvx_vec_fast_sigmoid_fp32_guard(sline, one, max_exp, min_exp);
|
||||
/* Prepare slinep for next iteration */
|
||||
slinep = slinec;
|
||||
}
|
||||
|
||||
if(step_of_1> 0){
|
||||
|
||||
slinec = htp_is_aligned(input_v_ptr, 128) && leftover == 0 ? slinep : *input_v_ptr++;
|
||||
sline = Q6_V_valign_VVR(slinec, slinep, (size_t) input);
|
||||
*((HVX_UVector *)(output_v_ptr++)) = hvx_vec_fast_sigmoid_fp32_guard(sline, one, max_exp, min_exp);;
|
||||
|
||||
slinep = slinec;
|
||||
}
|
||||
if(leftover> 0){
|
||||
slinec = (is_in_one_chunk(input_v_ptr, leftover_size, 128)
|
||||
? slinep
|
||||
: *input_v_ptr++);
|
||||
|
||||
sline = Q6_V_valign_VVR(slinec, slinep, (size_t) input);
|
||||
|
||||
HVX_Vector sout = hvx_vec_fast_sigmoid_fp32_guard(sline, one, max_exp, min_exp);
|
||||
hvx_vec_store_u(output_v_ptr, leftover_size, sout);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
float hvx_sum_of_squares_f32(const uint8_t * restrict src, const int num_elems);
|
||||
void hvx_mul_f32(const uint8_t * restrict src0,
|
||||
const uint8_t * restrict src1,
|
||||
|
|
|
|||
|
|
@ -798,6 +798,7 @@ static void htp_packet_callback(dspqueue_t queue, int error, void * context) {
|
|||
break;
|
||||
|
||||
case HTP_OP_UNARY_SILU:
|
||||
case HTP_OP_UNARY_GELU:
|
||||
if (n_bufs != 2) {
|
||||
FARF(ERROR, "Bad act-req buffer list");
|
||||
continue;
|
||||
|
|
|
|||
Loading…
Reference in New Issue