Fix launch logic when supports_cooperative_launch=false
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@ -407,15 +407,13 @@ static void soft_max_f32_cuda(const float * x,
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// Parallelize across SMs for top-p/dist-smapling
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// The heuristic for parallelizing rows across SMs vs parallelizing single row & looping over all rows was done on the basis of a B6000 GPU and
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// Can be adapted further for lower-SM-count GPUs, though keeping data in registers should be implemented first as that is the optimal solution.
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if (ncols_x / (params.ne01 * params.ne02 * params.ne03) > 8192 && mask == nullptr && sinks == nullptr && params.scale == 1.0f && params.max_bias == 0.0f) {
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if (ggml_cuda_info().devices[id].supports_cooperative_launch) {
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if (ggml_cuda_info().devices[id].supports_cooperative_launch && ncols_x / (params.ne01 * params.ne02 * params.ne03) > 8192 && mask == nullptr && sinks == nullptr && params.scale == 1.0f && params.max_bias == 0.0f) {
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ggml_cuda_pool_alloc<float> tmp_alloc(ctx.pool(), ggml_cuda_info().devices[id].nsm * sizeof(float));
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void * kernel_args[] = { (void *) &x, (void *) &dst, (void *) &tmp_alloc.ptr, (void *) const_cast<soft_max_params *>(& params)};
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CUDA_CHECK(cudaLaunchCooperativeKernel((void *) soft_max_f32_parallelize_cols,
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dim3(ggml_cuda_info().devices[id].nsm, 1, 1),
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dim3(WARP_SIZE * 8, 1, 1), kernel_args, 0, stream));
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}
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} else {
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const size_t nbytes_shared_low = WARP_SIZE * sizeof(float);
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soft_max_f32<false, 0, 0>
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